COM20019I_0610 Datasheet, PDF (26/70 Pages) SMSC Corporation – Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

RAM
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip
ADDR MSB
00
RI/TR1
0
01
C7
C6
02
RD-
AUTO-
DATA
INC
03
A7
A6
Table 6.2 - Write Register Summary
WRITE
0
0
EXCNAK RECON
NEW
NEXTID
C5
C4
C3
C2
C1
0
0
0
A10
A9
A5
A4
A3
A2
A1
04
D7
D6
D5
D4
05
(R/W)* (R/W)*
0
0
06 RESET CCHEN TXEN ET1
07-0
TID7
TID6
07-1
NID7
NID6
07-2
P1-
FOUR
MODE _NAKS
07-3
0
0
07-4 RBUS-
0
TMG
TID5
NID5
0
0
0
TID4
NID4
RCV-
ALL
0
0
D3
0
ET2
TID3
NID3
CKP3
D2
SUB-AD2
BACK-
PLANE
TID2
NID2
CKP2
D1
SUB-
AD1
SUB-
AD1
TID1
NID1
CKP1
0
0
0
EF
NO-
RCN-
SYNC
TM1
Note*:(R/W) These bits can be Written or Read. For more information see Appendix C.
LSB
TA/
TTA
C0
A8
A0
D0
SUB-
AD0
SUB-
AD0
TID0
NID0
SLOW-
ARB
0
RCN-
TM0
REGISTER
INTERRUPT
MASK
COMMAND
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
DATA
SUBADR
CONFIG-
URATION
TENTID
NODEID
SETUP1
TEST
SETUP2
6.2
INTERNAL REGISTERS
The COM20019I 3V contains 14 internal registers. Tables 2 and 3 illustrate the COM20019I 3V register
map. All undefined bits are read as undefined and must be written as logic "0".
6.2.1 Interrupt Mask Register (IMR)
The COM20019I 3V is capable of generating an interrupt signal when certain status bits become true. A
write to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the
IMR are in the same position as their corresponding status bits in the Status Register and Diagnostic
Status Register. A logic "1" in a particular position enables the corresponding interrupt. The Status bits
capable of generating an interrupt include the Receiver Inhibited bit, New Next ID bit, Excessive NAK bit,
Reconfiguration Timer bit, and Transmitter Available bit. No other Status or Diagnostic Status bits can
generate an interrupt.
The six maskable status bits are ANDed with their respective mask bits, and the results are ORed to
produce the interrupt signal. An RI or TA interrupt is masked when the corresponding mask bit is reset
to logic "0", but will reappear when the corresponding mask bit is set to logic "1" again, unless the interrupt
status condition has been cleared by this time. A RECON interrupt is cleared when the "Clear Flags"
command is issued. An EXCNAK interrupt is cleared when the "POR Clear Flags" command is issued. A
New Next ID interrupt is cleared by reading the Next ID Register. The Interrupt Mask Register defaults to
the value 0000 0000 upon hardware reset.
Rev. 10-31-06
Page 26
DATASHEET
SMSC COM20019I 3.3V Rev.C