COM20019I_0610 Datasheet, PDF (42/70 Pages) SMSC Corporation – Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

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Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip
ƒ The traditional TA and RI bits are still available to reflect the present status of the device.
6.5.1 Transmit Command Chaining
When the processor issues the first "Enable Transmit to Page fnn" command, the COM20019I 3V
responds in the usual manner by resetting the TA and TMA bits to prepare for the transmission from the
specified page. The TA bit can be used to see if there is currently a transmission pending, but the TA bit is
really meant to be used in the non-chaining mode only. The TTA bits provide the relevant information for
the device in the Command Chaining mode.
In the Command Chaining Mode, at any time after the first command is issued, the processor can issue a
second "Enable Transmit from Page fnn" command. The COM20019I 3V stores the fact that the second
transmit command was issued, along with the page number.
After the first transmission is completed, the COM20019I 3V updates the Status Register by setting the
TTA bit, which generates an interrupt. The interrupt service routine should read the Status Register. At
this point, the TTA bit will be found to be a logic "1" and the TMA (Transmit Message Acknowledge) bit will
tell the processor whether the transmission was successful. After reading the Status Register, the "Clear
Transmit Interrupt" command is issued, thus resetting the TTA bit and clearing the interrupt. Note that
only the "Clear Transmit Interrupt" command will clear the TTA bit and the interrupt. It is not necessary,
however, to clear the bit or the interrupt right away because the status of the transmit operation is double
buffered in order to retain the results of the first transmission for analysis by the processor. This
information will remain in the Status Register until the "Clear Transmit Interrupt" command is issued. Note
that the interrupt will remain active until the command is issued, and the second interrupt will not occur
until the first interrupt is acknowledged. The COM20019I 3V guarantees a minimum of 200nS (at EF=1)
interrupt inactive time interval between interrupts. The TMA bit is also double buffered to reflect whether
the appropriate transmission was a success. The TMA bit should only be considered valid after the
corresponding TTA bit has been set to a logic "1". The TMA bit never causes an interrupt.
When the token is received again, the second transmission will be automatically initiated after the first is
completed by using the stored "Enable Transmit from Page fnn" command. The operation is as if a new
"Enable Transmit from Page fnn" command has just been issued. After the first Transmit status bits are
cleared, the Status Register will again be updated with the results of the second transmission and a
second interrupt resulting from the second transmission will occur. The COM20019I 3V guarantees a
minimum of 200ns (at EF=1) interrupt inactive time interval before the following edge.
The Transmitter Available (TA) bit of the Interrupt Mask Register now masks only the TTA bit of the Status
Register, not the TA bit as in the non-chaining mode. Since the TTA bit is only set upon transmission of a
packet (not by RESET), and since the TTA bit may easily be reset by issuing a "Clear Transmit Interrupt"
command, there is no need to use the TA bit of the Interrupt Mask Register to mask interrupts generated
by the TTA bit of the Status Register.
In Command Chaining mode, the "Disable Transmitter" command will cancel the oldest transmission. This
permits canceling a packet destined for a node not ready to receive. If both packets should be canceled,
two "Disable Transmitter" commands should be issued.
6.5.2 Receive Command Chaining
Like the Transmit Command Chaining operation, the processor can issue two consecutive "Enable
Receive from Page fnn" commands.
After the first packet is received into the first specified page, the TRI bit of the Status Register will be set to
logic "1", causing an interrupt. Again, the interrupt need not be serviced immediately. Typically, the
interrupt service routine will read the Status Register. At this point, the RI bit will be found to be a logic "1".
After reading the Status Register, the "Clear Receive Interrupt" command should be issued, thus resetting
the TRI bit and clearing the interrupt. Note that only the "Clear Receive Interrupt" command will clear the
Rev. 10-31-06
Page 42
DATASHEET
SMSC COM20019I 3.3V Rev.C