COM20019I_0610 Datasheet, PDF (60/70 Pages) SMSC Corporation – Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

RAM
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip
A0-A2
nCS
DIR
nDS
D0-D7
t1
t3
t5
VALID
t2
t4
t7
t10
t8
t11
Note 2
t6**
t9
t6
VALID DATA
Parameter
t1 Address Setup to nDS Active
t2 Address Hold from nDS Inactive
t3 nCS Setup to nDS Active
t4 nCS Hold from nDS Inactive
t5 DIR Setup to nDS Active
t6 Cycle Time (nDS to Next Time )**
t7 DIR Hold from nDS Inactive
t8 Valid Data Setup to nDS High
t9 Data Hold from nDS High
t10 nDS Low Width
t11 nDS High Width
min
15
10
5
0
10
4TARB*
10
30***
10
20
20
max
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
***: nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available.
Note 1: The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
**Note 2: Any cycle occurring after a write to the Address Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nDS to the leading edge
of the next nDS.
Write cycle for Address Pointer Low Registers occurring after an access to
Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
Figure 8.11 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE
Rev. 10-31-06
Page 60
DATASHEET
SMSC COM20019I 3.3V Rev.C