LAN9730 Datasheet, PDF (8/61 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

High-Speed Inter-Chip (HSIC) USB 2.0 to 10/100 Ethernet Controller
Datasheet
1.2.1
1.2.2
1.2.3
USB
The USB portion of the LAN9730/LAN9730i integrates a Hi-Speed USB 2.0 device controller and HSIC
interface.
The USB device controller (UDC) contains a USB low-level protocol interpreter which implements the
USB bus protocol, packet generation/extraction, PID/Device ID parsing and CRC coding/decoding, with
autonomous error handling. The USB device controller is capable of operating in USB 2.0 Hi-Speed
mode and contains autonomous protocol handling functions such as handling of suspend/resume/reset
conditions, remote wakeup, and stall condition clearing on Setup packets. The USB device controller
also autonomously handles error conditions such as retry for CRC and data toggle errors, and
generates NYET, STALL, ACK and NACK handshake responses, depending on the Endpoint buffer
status.
The LAN9730/LAN9730i implements four USB Endpoints: Control, Interrupt, Bulk-in, and Bulk-out. The
Bulk-in and Bulk-out Endpoints allow for Ethernet reception and transmission respectively.
Implementation of vendor-specific commands allows for efficient statistics gathering and access to the
device’s system control and status registers.
The integrated HSIC interface is compliant with the High-Speed Interchip USB Electrical Specification
Revision 1.0 (09-23-07) and supports the Hi-Speed mode of operation.
FIFO Controller
The FIFO controller uses an internal SRAM to buffer RX and TX traffic. Bulk-out packets from the USB
controller are directly stored into the TX buffer. Ethernet frames are directly stored into the RX buffer
and become the basis for bulk-in packets.
Ethernet
LAN9730/LAN9730i integrates an IEEE 802.3 PHY for twisted pair Ethernet applications and a 10/100
Ethernet Media Access Controller (MAC).
The PHY can be configured for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet
operation in either Full or Half Duplex configurations. The PHY block includes auto-negotiation, auto-
polarity correction, and Auto-MDIX. Minimal external components are required for the utilization of the
Integrated PHY.
Optionally, an external PHY may be used via the MII (Media Independent Interface) port, effectively
bypassing the internal PHY. This option allows support for HomePNA and HomePlug applications.
The Ethernet MAC/PHY supports numerous power management wakeup features, including Magic
Packet, Wake on LAN and Link Status Change. Eight wakeup frame filters are provided by the device.
Revision 1.1 (05-13-13)
8
DATASHEET
SMSC LAN9730/LAN9730i