LAN9730 Datasheet, PDF (38/61 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

High-Speed Inter-Chip (HSIC) USB 2.0 to 10/100 Ethernet Controller
Datasheet
The Host processor is connected to a Chipset containing the USB Host Controller (HC). The USB Host
Controller interfaces to the device via the HSIC USB signals. An Embedded Controller (EC) signals
the Chipset and the Host processor to power up via an Enable signal. The EC interfaces to the device
via three signals. The PME signal is an input to the EC from the device that indicates the occurrence
of a wakeup event. The PME_CLEAR (nRESET) signal is used to clear the PME. The
PME_MODE_SEL signal is sampled by the device when PME_CLEAR (nRESET) is asserted and is
used by the device to determine whether it should remain in PME Mode or resume normal operation.
GPIO pins are used for PME handling. The pins used depend on the value of the PHY_SEL pin, which
determines PHY Mode of operation. In Internal PHY Mode of operation, GPIO0 is reserved for use as
an output to signal the PME. GPIO1 is reserved for use as the PME_MODE_SEL input. GPIO8 and
GPIO9 are reserved for analogous use, respectively, in External PHY Mode of operation.
The application scenario in Figure 5.1 assumes that the Host processor and the Chipset are powered
off, the EC is operational, and the device is in PME Mode, waiting for a wake event to occur. A wake
event will result in the device signaling a PME event to the EC, which will then wake up the Host
processor and Chipset via the Enable signal. The EC sets PME_MODE_SEL to determine whether the
device is to begin normal operation or continue in PME Mode, and asserts PME_CLEAR (nRESET) to
clear the PME.
The following wake events are supported:
 Wakeup Pin(s)
The GPIO pins not reserved for PME handling have the capability to wake up the device when
operating in PME Mode. In order for a GPIO to generate a wake event, its enable bit must be set
in the GPIO10:8 Wakeup Enables or GPIO7:0 Wakeup Enables bytes of the EEPROM, as
appropriate. During PME Mode of operation, the GPIOs used for signaling (GPIOs 0 and 1 or
GPIOs 8 and 9) are not affected by the values set in the corresponding bits of GPIO10:8 Wakeup
Enables or GPIO7:0 Wakeup Enables.
GPIO10 is available as a wakeup pin in External PHY Mode, while GPIOs 2-10 are available in
Internal PHY Mode. The GPIO10 Detection Select bit in the GPIO PME Flags byte of the EEPROM
sets the detection mode for GPIO10 in both External and Internal PHY Mode (if set in GPIO10:8
Wakeup Enables), while GPIOs 2-9 are active low (by default) when operating in Internal PHY
Mode.
 Magic Packet
Reception of a Magic Packet when in PME Mode will result in a PME being asserted.
 PHY Link Up
Detection of a PHY link partner when in PME Mode will result in a PME being asserted.
In order to facilitate PME Mode of operation, the GPIO PME Enable bit in the GPIO PME Flags field,
must be set and all remaining GPIO PME Flags field bits must be appropriately configured for pulse
or level signaling, buffer type and GPIO PME WOL selection. The PME event is signaled on GPIO0
(External PHY Mode) or GPIO8, depending on the PHY Mode of operation.
The PME_MODE_SEL pin (GPIO1 in Internal Mode of operation, GPIO9 in External Mode of
operation) must be driven to the value that determines whether or not the device remains in PME Mode
of operation (1) or resumes normal operation (0) when the PME is recognized and cleared by the EC
via PME_CLEAR (nRESET) assertion.
Note: When in PME Mode, nRESET or POR will always cause the contents of the EEPROM to be
reloaded.
Note: GPIO10 may be used in PME and External PHY Mode to connect to an external PHY’s Link
LED, in order to generate a PHY Link Up wake event.
Revision 1.1 (05-13-13)
38
DATASHEET
SMSC LAN9730/LAN9730i