LAN9730 Datasheet, PDF (30/61 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

High-Speed Inter-Chip (HSIC) USB 2.0 to 10/100 Ethernet Controller
Datasheet
BITS
1
0
Table 4.3 GPIO PME Flags (continued)
DESCRIPTION
GPIO10 Detection Select
This bit selects the detection mode for GPIO10 when operating in PME Mode. In PME Mode, GPIO10
is usable in both Internal and External PHY Mode as a wakeup pin. This parameter defines whether
the wakeup should occur on an active high or active low signal.
0 = Active-low detection for GPIO10
1 = Active-high detection for GPIO10
Note: If GPIO PME Enable is 0, this bit is ignored.
RESERVED
4.2
EEPROM Defaults
The signature value of 0xA5 is stored at address 0. A different signature value indicates to the
EEPROM controller that no EEPROM or an un-programmed EEPROM is attached to the device. In
this case, the hardware default values are used, as shown in Table 4.4.
Table 4.4 EEPROM Defaults
FIELD
DEFAULT VALUE
MAC Address
Full-Speed Polling Interval (ms)
Hi-Speed Polling Interval (ms)
Configuration Flags
Maximum Power (mA)
Vendor ID
Product ID
FFFFFFFFFFFFh
01h
04h
04h
FAh
0424h
9730h
Note: The Configuration Flags are affected by the RMT_WKP strap.
4.3
EEPROM Auto-Load
Certain system level resets (USB reset, POR, nRESET and SRST) cause the EEPROM contents to
be loaded into the device. After a reset, the EEPROM controller attempts to read the first byte of data
from the EEPROM. If the value 0xA5 is read from the first address, then the EEPROM controller will
assume that an external Serial EEPROM is present.
Note: The USB reset only loads the MAC address.
Revision 1.1 (05-13-13)
30
DATASHEET
SMSC LAN9730/LAN9730i