LAN9730 Datasheet, PDF (7/61 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

Chapter 1 Introduction
High-Speed Inter-Chip (HSIC) USB 2.0 to 10/100 Ethernet Controller
Datasheet
1.1
Block Diagram
HSIC
HSIC
Interface
USB 2.0
Device
Controller
FIFO
Controller
10/100
Ethernet
MAC
Ethernet
PHY
Ethernet
MII: To optional
external PHY
JTAG
TAP
Controller
LAN9730/LAN9730i
SRAM
EEPROM
Controller
Figure 1.1 LAN9730/LAN9730i Block Diagram
EEPROM
1.2
Overview
The LAN9730/LAN9730i is a high performance solution for USB to 10/100 Ethernet port bridging. With
applications ranging from embedded systems, set-top boxes, and PVRs, to USB port replicators, and
test instrumentation, the device is targeted as a high-performance, low-cost USB/Ethernet connectivity
solution.
The LAN9730/LAN9730i contains an integrated 10/100 Ethernet PHY, HSIC interface, Hi-Speed USB
2.0 device controller, 10/100 Ethernet MAC, TAP controller, EEPROM controller, and a FIFO controller
with a total of 30 kB of internal packet buffering.
The internal USB 2.0 device controller is compliant with the USB 2.0 Hi-Speed standard. The HSIC
interface is compliant with the High-Speed Interchip USB Electrical Specification Revision 1.0. High-
Speed Inter-Chip (HSIC) is a digital interconnect bus that enables the use of USB technology as a low-
power chip-to-chip interconnect at speeds up to 480 Mb/s. The device implements Control, Interrupt,
Bulk-in and Bulk-out USB Endpoints.
The Ethernet controller supports auto-negotiation, auto-polarity correction, HP Auto-MDIX, and is
compliant with the IEEE 802.3 and 802.3u standards. An external MII interface provides support for
an external Fast Ethernet PHY, HomePNA, and HomePlug functionality.
Multiple power management features are provided, including various low-power modes, and Magic
Packet, Wake On LAN and Link Status Change wake events. These wake events can be programmed
to initiate a USB remote wakeup. A PCI-like PME wake is also supported when the Host controller is
disabled.
An internal EEPROM controller exists to load various USB configuration information and the device
MAC address. The integrated IEEE 1149.1 compliant TAP controller provides boundary scan via JTAG.
SMSC LAN9730/LAN9730i
7
DATASHEET
Revision 1.1 (05-13-13)