LAN9730 Datasheet, PDF (53/61 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

High-Speed Inter-Chip (HSIC) USB 2.0 to 10/100 Ethernet Controller
Datasheet
6.5.6
MII Interface Timing
This section specifies the MII interface transmit and receive timing.
Note: The MII timing adheres to the IEEE 802.3 specification. Refer to the IEEE 802.3 specification
for additional MII timing information.
TXCLK
(INPUT)
t_clkp
t_clkh t_clkl
t_val
t_val
t_invld
TXD[3:0]
(OUTPUT)
t_invld
t_val
TXEN, TXER
(OUTPUT)
Figure 6.6 MII Transmit Timing
Table 6.18 MII Transmit Timing Values
SYMBOL
t_clkp
t_clkh
t_clkl
t_val
t_invld
DESCRIPTION
TXCLK period
TXCLK high time
TXCLK low time
TXD[3:0], TXEN, TXER output valid from rising
edge of TXCLK
TXD[3:0], TXEN, TXER output invalid from
rising edge of TXCLK
MIN
40
t_clkp*0.4
t_clkp*0.4
0
MAX
t_clkp*0.6
t_clkp*0.6
22.0
UNITS
ns
ns
ns
ns
NOTES
Note 6.11
ns
Note 6.11
Note 6.11 Timing was designed for a system load between 10 pf and 25 pf.
SMSC LAN9730/LAN9730i
53
DATASHEET
Revision 1.1 (05-13-13)