LAN9730 Datasheet, PDF (52/61 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

High-Speed Inter-Chip (HSIC) USB 2.0 to 10/100 Ethernet Controller
Datasheet
6.5.5
EEPROM Timing
The following specifies the EEPROM timing requirements for the device:
EECS
EECLK
t_cshckh
t_ckcyc
t_ckh t_ckl
t_csl
t_cklcsl
EEDO
EEDI
EEDI (VERIFY)
t_dvckh ^tckhinvld
t_dsckh
t_cshdv
t_dhckh
t_dhcsl
Figure 6.5 EEPROM Timing
SYMBOL
t_ckcyc
t_ckh
t_ckl
t_cshckh
t_cklcsl
t_dvckh
t_ckhinvld
t_dsckh
t_dhckh
t_cshdv
t_dhcsl
t_csl
Table 6.17 EEPROM Timing Values
DESCRIPTION
EECLK cycle time
EECLK high time
EECLK low time
EECS high before rising edge of EECLK
EECLK falling edge to EECS low
EEDO valid before rising edge of EECLK
EEDO invalid after rising edge EECLK
EEDI setup to rising edge of EECLK
EEDI hold after rising edge of EECLK
EEDIO valid after EECS high (VERIFY)
EEDIO hold after EECS low (VERIFY)
EECS low
MIN
1110
550
550
1070
30
550
550
90
0
0
1070
TYP
MAX
1130
570
570
600
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Revision 1.1 (05-13-13)
52
DATASHEET
SMSC LAN9730/LAN9730i