LAN9730 Datasheet, PDF (17/61 Pages) SMSC Corporation – High-Speed Inter-Chip (HSIC) USB 2.0

High-Speed Inter-Chip (HSIC) USB 2.0 to 10/100 Ethernet Controller
Datasheet
NUM PINS
NAME
1
JTAG Test
Port Reset
(Internal PHY
Mode)
Receive Data
0
(External
PHY Mode)
1
JTAG Test
Data Out
(Internal PHY
Mode)
PHY Reset
(External
PHY Mode)
1
JTAG Test
Clock
(Internal PHY
Mode)
Receive Data
1
(External
PHY Mode)
1
JTAG Test
Mode Select
(Internal PHY
Mode)
Receive Data
2
(External
PHY Mode)
1
JTAG Test
Data Input
(Internal PHY
Mode)
Receive Data
3
(External
PHY Mode)
Table 2.3 JTAG Pins
SYMBOL
BUFFER
TYPE
DESCRIPTION
nTRST
IS
(PU)
In Internal PHY Mode, this active-low pin
functions as the JTAG test port reset input.
RXD0
IS
(PD)
In External PHY Mode, this pin functions as the
receive data 0 input from the external PHY.
TDO
O8
In Internal PHY Mode, this pin functions as the
JTAG data output.
nPHY_RST
TCK
RXD1
O8
In External PHY Mode, this active-low pin
functions as the PHY reset output.
IS
(PU)
In Internal PHY Mode, this pin functions as the
JTAG test clock. The maximum operating
frequency of this clock is 25 MHz.
IS
(PD)
In External PHY Mode, this pin functions as the
receive data 1 input from the external PHY.
TMS
IS
(PU)
In Internal PHY Mode, this pin functions as the
JTAG test mode select.
RXD2
IS
(PD)
In External PHY Mode, this pin functions as the
receive data 2 input from the external PHY.
TDI
IS
In Internal PHY Mode, this pin functions as the
(PU)
JTAG data input.
RXD3
IS
(PD)
In External PHY Mode, this pin functions as the
receive data 3 input from the external PHY.
SMSC LAN9730/LAN9730i
17
DATASHEET
Revision 1.1 (05-13-13)