COM200221 Datasheet, PDF (76/82 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Table 8.1 - DMA Timing
PARAMETER
MIN TYP
t1 nDACK Inactive Pulse Width
t2 The First DREQ Assertion Delay After Writing Low
Pointer
4 Tarb 5
Tarb
t3 DREQ Assert Delay from nREFEX Active at
0
Programmable Burst Transfer Mode
t4 DREQ Assertion Delay from Write/Read Inactive at Non-
0
Burst Transfer Mode
t5 DREQ Assertion Delay from nDACK
Inactive due to Timeout of Gate Timer
at Programmable Burst Transfer Mode
GTTM
bit =0
GTTM bit=1
7Txtl
15Txtl
t6 DREQ Negation Delay from Write/Read Active
0
t7 DREQ Negation Delay from TC and Write/Read Active
0
t8 Data Access Time from Read Active
t9 Data Float Delay from Read Inactive
0
t10 nREFEX Active Pulse Width
20
t11 Write Active Pulse Width
CASE 1W
20
MAX
30
5Tarb
+40ns
40
40
8Txtl
+40ns
16Txtl
+40ns
40
40
40
20
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
CASE 2W
65
ns
t12 Read Active Pulse Width
CASE 1R
60
ns
CASE 2R
100
ns
t13 Active Pulse Overlap Width between TC and Write/Read
20
ns
t14 Write/Read Inactive Pulse Width
CASE1w/1R
20
ns
CASE2w/2R
30
ns
t15 Write Cycle Interval Period
4Tarb
t16 Read Cycle Interval Period
CASE1R
4Tarb
CASE2R
4Tarb+3
0nS
t17 Data Setup to Write Inactive
30
ns
t18 Data Hold From Write Inactive
10
ns
t19 nCS High Setup to nDACK Active
20
ns
t20 nCS High Hold from nDACK Inactive
20
ns
t21 DREQ Active Setup to nDACK Active
20
ns
t22 DIR Setup to nDS Low (Motorola mode only)
10
ns
t23 DIR Hold from nDS High (Motorola mode only)
10
ns
t24 nDACK Setup to Write/Read Active
30
ns
t25 nDACK Hold After Write/Read Inactive
5
ns
t26 nREFEX Inactive Time
3Txtl
Notes:
1. Tarb is the ARBITRATION CLOCK PERIOD. It depends on Topr and SLOWARB bit.
SLOWARB must set to “1” if the data rate is over 5 Mbps. (i.e. 10 Mbps)
Tarb is Topr at SLOWARB=0 and Tarb is 2Topr at SLOWARB=1.
Topr is the period of Operation Clock Frequency. It depends on the CKUP1 and CKUP0 bits.
2. Txtl is a period of external XTAL oscillation frequency.
3. The nREFEX pin must not be Low while nDACK is Low.
NOTE
Note 1
Note 3
Note 4
Note 2
Note 4
Note 4
Note 4
Note 4
Note
4,5
Note
4,5
Note 4
Note
4,5
Note
1,4
Note
1,4,5
Note 4
Note 4
Note 4
Note 4
Note 2
Revision 09-27-07
Page 76
DATASHEET
SMSC COM20022I