COM200221 Datasheet, PDF (11/82 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Chapter 4 Protocol Description
4.1
Network Protocol
Communication on the network is based on a token passing protocol. Establishment of the network
configuration and management of the network protocol are handled entirely by the COM20022I's internal
microcoded sequencer. A processor or intelligent peripheral transmits data by simply loading a data packet
and its destination ID into the COM20022I's internal RAM buffer, and issuing a command to enable the
transmitter. When the COM20022I next receives the token, it verifies that the receiving node is ready by
first transmitting a FREE BUFFER ENQUIRY message. If the receiving node transmits an ACKnowledge
message, the data packet is transmitted followed by a 16-bit CRC. If the receiving node cannot accept the
packet (typically its receiver is inhibited), it transmits a Negative AcKnowledge message and the
transmitter passes the token. Once it has been established that the receiving node can accept the packet
and transmission is complete, the receiving node verifies the packet. If the packet is received
successfully, the receiving node transmits an ACKnowledge message (or nothing if it is not received
successfully) allowing the transmitter to set the appropriate status bits to indicate successful or unsuccessful
delivery of the packet. An interrupt mask permits the COM20022I to generate an interrupt to the processor
when selected status bits become true. Figure 2.1 is a flow chart illustrating the internal operation of the
COM20022I connected to a 20 MHz crystal oscillator.
4.2
Data Rates
The COM20022I is capable of supporting data rates from 156.25 Kbps to 10 Mbps. The following protocol
description assumes a 10 Mbps data rate. To attain the faster data rates, the clock frequency may be
doubled or quadrupled by the internal clock multiplier (see next section). For slower data rates, an internal
clock divider scales down the clock frequency. Thus all timeout values are scaled as shown in the
following table:
Example:
IDLE LINE Timeout @ 10 Mbps = 20.5 μs. IDLE LINE Timeout for 156.2 Kbps is 20.5 μs * 64 = 1.3 ms
INTERNAL CLOCK
FREQUENCY
80 MHz
40 MHz
20 MHz
CLOCK PRESCALER
Div. by 8
Div. by 8
Div. by 8
Div. by 16
Div. by 32
Div. by 64
Div. by 128
DATA RATE
10 Mbps
5 Mbps
2.5 Mbps
1.25 Mbps
625 Kbps
312.5 Kbps
156.25 Kbps
TIMEOUT SCALING FACTOR
(MULTIPLY BY)
1
2
4
8
16
32
64
SMSC COM20022I
Page 11
DATASHEET
Revision 09-27-07