COM200221 Datasheet, PDF (41/82 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
BIT
BIT NAME
7-0 Address 7-0
Table 6.7 - Address Pointer Low Register
SYMBOL
A7-A0
SWAP
DESCRIPTION
These bits hold the lower 8 address bits which provide the
addresses to RAM.
When 16 bit access is enabled, (W16=1), A0 becomes the SWAP
bit. Swap bit is undefined after a hardware reset. The swap bit
must be set before W16 bit is set to “1”. The swap bit is used to
swap the upper and lower data byte. The swap bit influences
both CPU cycle and DMA cycle. See Table Below.
Detected Host Interface
Mode
Swap Bit
D15-D8 D7-D0 Pin
Pin
Intel 80xx Mode
0
Odd
Even
(RD, WR Mode)
1
Even
Odd
Motorola 68xx Mode
0
Even
Odd
(DIR, DS Mode)
1
Odd
Even
BIT
7-3
2,1,0
BIT NAME
Reserved
Sub Address 2,1,0
Table 6.8 - Sub Address Register
SYMBOL
SUBAD
2,1,0
DESCRIPTION
These bits are undefined.
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD2 SUBAD1 SUBAD0 Register
0
0
0
Tentative ID \ (Same
0
0
1
Node ID \ as in
0
1
0
Setup 1 / Config
0
1
1
Next ID
/ Register)
1
0
0
Setup 2
1
0
1
Bus Control
1
1
0
DMA Count
1
1
1
Reserved
SUBAD1 and SUBAD0 are exactly the same as exist in the
Configuration Register. SUBAD2 is cleared automatically by writing
the Configuration Register.
SMSC COM20022I
Page 41
DATASHEET
Revision 09-27-07