COM200221 Datasheet, PDF (61/82 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
AD0-AD2,
D3-D15
nCS
ALE
nDS
VALID
t1
t2,
t4
t3
t11
t5
DIR
nIOCS16
Previous Value
t16
t9
t15
Invalid
VALID DATA
t12
t7
t6
Note 2
t8**
t13
t14
t8
t10
Valid Value
MUST BE: BUSTMG pin = HIGH
Parameter
min
max units
t1 Address Setup to ALE Low
t2 Address Hold from ALE Low
t3 nCS Setup to ALE Low
t4 nCS Hold from ALE Low
t5 ALE Low to nDS Low
t6 Valid Data Setup to nDS High
t7 Data Hold from nDS High
t8 Cycle Time (nDS to Next )**
t9 DIR Setup to nDS Active
t10 DIR Hold from nDS Inactive
t11 ALE High Width
t12 ALE Low Width
t13 nDS Low Width
t14 nDS High Width
t15 nIOCS16 Hold Delay from ALE Low
t16 nIOCS16 Output Delay from ALE Low
20
nS
10
nS
10
nS
10
nS
15
nS
30
nS
10
nS
4TARB*
nS
10
nS
10
nS
20
nS
20
nS
20
nS
20
nS
0
nS
40
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 1: The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
** Note 2:
Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4TARB from the trailing edge of nDS to the leading edge of the
next nDS.
Write cycle for Address Pointer Low Register occurring after an access to
Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
Note 2 is applied to an access to Data Register by DMA transfer.
Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals Write Cycle
SMSC COM20022I
Page 61
DATASHEET
Revision 09-27-07