COM200221 Datasheet, PDF (65/82 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
A0-A2
VALID
t1
t2
nCS
DIR
nDS
D0-D15
nIOCS16
t3
t5
t8
t12
t4
t6
t10
VALID DATA
VALID VALUE
t7
t11
t9 ^{Note 2}
t13
CASE 1: BUSTMG pin = HIGH and RBUSTMG bit = 0
Parameter
min
max units
t1 Address Setup to nDS Active
t2 Address Hold from nDS Inactive
t3 nCS Setup to nDS Active
t4 nCS Hold from nDS Inactive
t5 DIR Setup to nDS Active
t6 Cycle Time (nDS Low to Next Time Low)
t7 DIR Hold from nDS Inactive
t8 nDS Low to Valid Data
t9 nDS High to Data High Impedence
t10 nDS Low Width
t11 nDS High Width
t12 nIOCS16 Output Delay from nCS Low
t13 nIOCS16 Hold Delay from nCS High
15
nS
10
nS
5**
nS
0
nS
10
nS
4TARB*
nS
10
nS
40** nS
0
20
nS
60
nS
20
0****
nS
40*** ^nS
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
** nCS may become active after control becomes active, but the access time (t8) will
now be 45nS measured from the leading edge of nCS.
*** t12 is measured from the latest active (valid) timing among nCS, A0-A2.
**** _{t13 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.}
Note 1: The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
Note 2 is applied to an access to Data Register by DMA transfer.
Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle
SMSC COM20022I
Page 65
DATASHEET
Revision 09-27-07