COM200221 Datasheet, PDF (36/82 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

6.3
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Bus Control Register
The Bus Control Register is new to the COM20022I. It is an 8-bit read/write register accessed when the
Sub Address Bits SUBAD[2:0] are set up accordingly (see the bit definitions of the Sub Address Register).
This register contains bits for control of the DMA functionality. The DRQPOL bit is used to set the active
polarity of the DREQ pin. The TCPOL bit is used to set the active polarity of TC pin.
The DMAMD[0,1] bits select the data transfer mode of the DMA, either non-burst, burst, Programmable-
Burst by timer or programmable burst by cycle counter.
This transfer mode influences to the timing the DREQ pin. The use of the ITCEN/RTRG bit transfer mode
dependent. ITCEN is the Internal Terminal Counter Enable. It is used to select whether the DMA is
terminated by external TC or by either internal or external TC. ITCEN is for Non-Burst or Burst mode.
RTRG selects the re-trigger mode as either external or internal. It is for the two Programmable-Burst
modes. If RTRG = 0, the deasserted DREQ pin is reasserted on the falling edge of the nREFEX pin. If
RTRG = 1, the deasserted DREQ pin is reasserted by the timeout of the internal timer (350 ns or 750 ns,
as selected by the GTTM bit.) See Figure below.
nREFEX
DREQ
nDACK
nWR/nRD
RTRG=0
DREQ
nDACK
nWR/nRD
RTRG=1
350/750ns
Figure 6.1 - Illustration of the Effect of RTRG Bit on DMA Timing
The use of the TC8/RSYN/GTTM bit is also transfer mode dependent. TC8 is bit 8 of the Terminal Count
register. RSYN is the refresh synchronous bit; it is used to select whether the DMA is started immediately
or after Refresh execution. GTTM is the Gate Time bit; it is used to select the gate time of the
Programmable-Burst transfer.
TC8 is for Non-Burst or Burst mode. RSYN and GTTM are for the two Programmable-Burst modes.
The W16 bit is used to enable/disable the 16 bit access.
6.4
DMA Count Register
The DMA COUNT Register is new to the COM20022I. It is an 8-bit read/write register accessed when the
Sub Address Bits SUBAD[2:0] are set up accordingly (see the bit definitions of the Sub Address Register).
This register contains bits for control of the DMA functionality. The TC7-TC0 /TIM7-TIM0 /CYC7-CYC0
bits have one of three functions depending on the DMA transfer mode. TC7-TC0 are for Non-Burst or
Burst mode. These are the lower 8 bits of the Terminal Count setting register (the MSB is in the Bus
Control Register). The TIM7-TIM0 bits are for setting the time of the continuous DMA transfer in
Programmable-Burst by Timer mode. The CYC7-CYC0 bits are for setting the cycle count value of the
continuous DMA transfer in Programmable-Burst by cycle mode.
Revision 09-27-07
Page 36
DATASHEET
SMSC COM20022I