COM200221 Datasheet, PDF (67/82 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
A0-A2
nCS
nRD
nWR
D0-D15
t1
t3
Note 3
t10
t11
VALID
t2
t4
t8
t9
t5
Note 2
t6
t5**
t7
t12
VALID DATA
nIOCS16
VALID VALUE
CASE 1: BUSTMG pin = HIGH
Parameter
t1 Address Setup to nWR Active
t2 Address Hold from nWR Inactive
t3 nCS Setup to WR Active
t4 nCS Hold from nWR Inactive
t5 Cycle Time (nWR to Next )**
t6 Valid Data Setup to nWR High
t7 Data Hold from nWR High
t8 nWR Low Width
t9 nWR High Width
t10 nRD to nWR Low
t11 nIOCS16 Output Delay from nCS Low
t12 nIOCS16 Hold Delay from nCS High
min
15
10
5
0
4TARB*
30***
10
20
20
20
0*****
max
40****
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
***: nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available.
**** t11 is measured from the latest active (valid) timing among nCS, A0-A2.
***** _{t12 is measured from the earliest inactive (invalid) timing among nCS, A0-A2.}
Note 1: The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
**Note _{2: Any cycle occurring after a write to the Address Pointer Low Register}
requires a minimum of 4TARB from the trailing edge of nWR to the leading edge
of the next nWR.
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.
Notes 2 and 3 are applied to an access to Data Register by DMA transfer.
Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle
SMSC COM20022I
Page 67
DATASHEET
Revision 09-27-07