COM200221 Datasheet, PDF (59/82 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Chapter 8 Timing Diagrams
AD0-AD2,
D3-D15
nCS
ALE
nDS
VALID
t1
t2,
t4
t3
t11
t6
t5
DIR
nIOCS16
Previous Value
t9
t15 ^t16
Invalid
VALID DATA
t12
t13
t8
Valid Value
t7
t14
Note 2
t10
MUST BE: BUSTMG pin = HIGH and RBUSTMG bit = 0
Parameter
min
max units
t1 Address Setup to ALE Low
t2 Address Hold from ALE Low
t3 nCS Setup to ALE Low
t4 nCS Hold from ALE Low
t5 ALE Low to nDS Low
t6 nDS Low to Valid Data
t7 nDS High to Data High Impedance
t8 Cycle Time (nDS Low to Next Time Low)
t9 DIR Setup to nDS Active
t10 DIR Hold from nDS Inactive
t11 ALE High Width
t12 ALE Low Width
t13 nDS Low Width
t14 nDS High Width
t15 nIOCS16 Hold Delay from ALE Low
t16 nIOCS16 Output Delay from ALE Low
20
nS
10
nS
10
nS
10
nS
15
nS
40
nS
0
20
nS
4TARB*
nS
10
nS
10
nS
20
nS
20
nS
60
nS
20
nS
0
nS
40
nS
* _{TARB is the Arbitration Clock Period}
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 1:
Note 2:
The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
Note 2 is applied to an access to Data Register by DMA transfer.
Figure 8.1 - Multiplexed Bus, 68XX-Like Control Signals; Read Cycle
SMSC COM20022I
Page 59
DATASHEET
Revision 09-27-07