COM200221 Datasheet, PDF (32/82 Pages) SMSC Corporation – 10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
ADDR MSB
00 RI/TR1
0
01
C7
C6
02
RD-
AUTO-
DATA
INC
03
A7
A6
Table 6.2 - Write Register Summary
WRITE
0
DMA EXCNAK RECON
END
C5
C4
C3
C2
0
0
DMAEN
A10
A5
A4
A3
A2
04
D7
D6
D5
D4
05
(R/W)*
0
0
0
06
RESET CCHEN TXEN
ET1
07-0
07-1
07-2
07-3
07-4
07-5
07-6
Note*:
TID7
NID7
P1-
MODE
0
RBUS-
TMG
W16
TC7/
TIM7/
CYC7
TID6
NID6
FOUR
NAKS
0
0
0
TC6/
TIM6/
CYC6
TID5
NID5
0
0
CKUP1
TID4
NID4
RCV-
ALL
0
CKUP0
ITCEN/
RTRG
TC5/
TIM5/
CYC5
TC8/
RSYN/
GTTM
TC4/
TIM4/
CYC4
This bit can be written and read.
D3
(R/W)*
ET2
TID3
NID3
CKP3
0
EF
DMA-
MD1
TC3/
TIM3/
CYC3
D2
SUB-
AD2
BACK-
PLANE
TID2
NID2
CKP2
0
NO-
SYNC
DMA-
MD0
TC2/
TIM2/
CYC2
NEW
NEXTID
C1
A9
A1
D1
SUB-
AD1
SUB-
AD1
TID1
NID1
CKP1
0
RCN-
TM1
TC-
POL
TC1/
TIM1/
CYC1
LSB
TA/
TTA
C0
A8
A0/
SWAP
D0
SUB-
AD0
SUB-
AD0
TID0
NID0
SLOW-
ARB
0
RCN-
TM0
DRQ-
POL
TC0/
TIM0/
CYC0
REGISTER
INTERRUPT
MASK
COMMAND
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
DATA*
SUBADR
CONFIG-
URATION
TENTID
NODEID
SETUP1
TEST
SETUP2
BUS
CONTROL
DMA COUNT
*DATA REGISTER AT 16 BIT ACCESS
REGISTER
BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT _ADDR
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DATA
D
D
D
D
D
D D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
04
15 14 13 12 11 10
6.2
Internal Registers
The COM20022I contains 16 internal registers. Table 6.1 and Table 6.2 illustrate the COM20022I register
map. All undefined bits are read as undefined and must be written as logic "0".
6.2.1 Interrupt Mask Register (IMR)
The COM20022I is capable of generating an interrupt signal when certain status bits become true. A write
to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR
are in the same position as their corresponding status bits in the Status Register and Diagnostic Status
Register. A logic "1" in a particular position enables the corresponding interrupt. The Status bits capable of
generating an interrupt include the Receiver Inhibited bit, DMAEND bit (new to the COM20022I), New Next
Revision 09-27-07
Page 32
DATASHEET
SMSC COM20022I