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SI5315B-C-GM Datasheet, PDF (9/54 Pages) Silicon Laboratories – SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER | |||
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Si5315
Table 3. AC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = â40 to 85 ºC)
Parameter
Symbol
Test Condition
Min Typ Max Units
LVCMOS Output Pins
Rise/Fall Times
tRF
CLOAD = 20 pf
â
25
â
ns
See Figure 2
LOSn Trigger Window
LOSTRIG
From last CKINn ï to
internal detection of LOSn
â
â
750 µs
Time to Clear LOL after LOS
Cleared
tCLRLOL
ï¯ï LOS to ï¯ LOL
Assume Fold=Fnew,
Stable XA-XB reference
â
10
â
ms
PLL Performance
Output Clock Skew
Phase Change Due to
Temperature Variation
tSKEW
ïï of CKOUTn to ïï CKOUTn
â
â
100 ps
tTEMP Maximum phase change from
â
300
500
ps
â40 to +85 °C
Lock Time
tLOCKHW ïï RST with valid CKIN to ï¯ï LOL; â
1200
â
ms
BW = 100 Hz
Closed Loop Jitter Peaking
Jitter Tolerance
JPK
JTOL
â 0.05 0.1 dB
See 4.2.3. "Jitter Toler- ns pk-
ance" on page 18.
pk
Minimum Reset Pulse Width
tRSTMIN
1
â
â
µs
Output Clock Initial Phase Step
tP_STEP
During clock switch CKIN > 19.44
MHz
â
100
200
ps
Holdover Frequency Historical
Averaging Time
tHISTAVG
â
6.7
â
sec
Holdover Frequency Historical
Delay Time
tHISTDEL
â 26.2
â
ms
Spurious Noise
SPSPUR
Max spur @ n x f3
(n > 1, n x f3 < 100 MHz)
â
â75
â dBc
Notes:
1. Assumes N3 does not equal 1. IF N3 = 1, CKNDC = 50 µs.
2. Refers to Si5315A speed grade.
3. Refers to Si5315B speed grade.
Rev. 1.0
9
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