SI5315B-C-GM Datasheet, PDF (36/54 Pages) Silicon Laboratories – SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER

Si5315
6.2. Output Clock Drivers
The Si5315 has a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS, CML,
and CMOS formats. The signal format is selected for both CKOUT1 and CKOUT2 outputs using the SFOUT [1:0]
pins. This modifies the output common mode and differential signal swing. See Table 2, “DC Characteristics” for
output driver specifications. The SFOUT [1:0] pins are three-level input pins, with the states designated as L
(ground), M (V_DD/2), and H (V_DD). Table 17 shows the signal formats based on the supply voltage and the type of
load being driven.
Table 17. Output Signal Format Selection (SFOUT)
SFOUT[1:0]
HL
HM
LH
LM
MH
ML
All Others
Signal Format
CML
LVDS
CMOS
Disabled
LVPECL
Low-swing LVDS
Reserved
Si5315
CKOUTn
Z0 = 50 
Z0 = 50 
100 
Rcvr
Figure 15. Typical Differential Output Circuit
Si5315
CKOUTn
CMOS
Logic
Optionally Tie CKOUTn
Outputs Together for Greater Strength
Figure 16. Typical CMOS Output Circuit (Tie CKOUTn+ and CKOUTn– Together)
For the CMOS setting (SFOUT = LH), both output pins drive single-ended in-phase signals. The CKOUT+/- can be
externally shorted together for greater drive strength specified in Table 2, “DC Characteristics”.
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Rev. 1.0