SI5315B-C-GM Datasheet, PDF (50/54 Pages) Silicon Laboratories – SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER

Si5315
13. PCB Land Pattern
Figure 25 illustrates the PCB land pattern for the Si5315. Figure 26 illustrates the recommended ground pad
layout. Table 22 lists the land pattern dimensions.
Figure 25. PCB Land Pattern
Figure 26. Ground Pad Recommended Layout
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Rev. 1.0