SI5315B-C-GM Datasheet, PDF (32/54 Pages) Silicon Laboratories – SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER

Si5315
Table 15. Lock Detect Retrigger Time
PLL Bandwidth Setting (BW)
60–120 Hz
Retrigger Time (ms)
53
120–240 Hz
240–480 Hz
480–960 Hz
960–1920 Hz
1920–3840 Hz
3840–7680 Hz
26.5
13.3
6.6
3.3
1.66
0.833
5.5. Holdover Mode
If an LOS condition exists on the selected input clock, the device enters holdover. In this mode, the device provides
a stable output frequency until the input clock returns and is validated. When the device enters holdover, the
internal oscillator is initially held to its last frequency value. Next, the internal oscillator slowly transitions to a
historical average frequency value that was taken over a time window of 6,711 ms in size that ended 26 ms before
the device entered holdover. This frequency value is taken from an internal memory location that keeps a record of
previous DSPLL frequency values. By using a historical average frequency, input clock phase and frequency
transients that may occur immediately preceding loss of clock or any event causing holdover do not affect the
holdover frequency. Also, noise related to input clock jitter or internal PLL jitter is minimized.
If a highly stable reference, such as an oven-controlled crystal oscillator, is supplied at XA/XB, an extremely stable
holdover can be achieved. If a crystal is supplied at the XA/XB port, the holdover stability will be limited by the
stability of the crystal; Table 3, “AC Characteristics” gives the specifications related to the holdover function.
5.5.1. Recovery from Holdover
When the input clock signal returns, the device transitions from holdover to the selected input clock. The device
performs hitless recovery from holdover. The clock transition from holdover to the returned input clock includes
"phase buildout" to absorb the phase difference between the holdover clock phase and the input clock phase. See
Table 3, “AC Characteristics” for specifications.
5.6. PLL Bypass Mode
The Si5315 supports a PLL bypass mode in which the selected input clock is fed directly to both enabled output
buffers, bypassing the DSPLL. Internally, the bypass path is implemented with high-speed differential signaling;
however, this path is not a low jitter path and will see significantly higher jitter on CKOUT. In PLL bypass mode, the
input and output clocks will be at the same frequency. PLL bypass mode is useful in a laboratory environment to
measure system performance with and without the jitter attenuation provided by the DSPLL. The DSBL2_BY pin is
used to select the PLL Bypass Mode according to Table 16. Bypass mode is not supported for CMOS clock outputs
(SFOUT = LH).
Table 16. DSBL2/BYPASS Pin Settings
DSBL2/BYPASS
L
M
H
Function
CKOUT2 Enabled
CKOUT2 Disabled
PLL Bypass Mode w/ CKOUT2 Enabled
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Rev. 1.0