SI5315B-C-GM Datasheet, PDF (46/54 Pages) Silicon Laboratories – SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER

Si5315
Pin #
27
26
25
24
29
28
33
30
34
35
36
GND
PAD
Pin Name
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
CKOUT1–
CKOUT1+
SFOUT0
SFOUT1
CKOUT2–
CKOUT2+
NC
GND
Table 19. Si5315 Pin Descriptions (Continued)
I/O Signal Level
Description
I
3-Level Frequency Select.
Three level inputs that select the input clock and clock multi-
plication ratio, depending on the FRQTBL setting.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
O
Multi
Clock Output 1.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML com-
patible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
I
3-Level Signal Format Select.
Three level inputs that select the output signal format (com-
mon mode voltage and differential swing) for both CKOUT1
and CKOUT2.
SFOUT[1:0]
Signal Format
HH
Reserved
HM
LVDS
HL
CML
MH
LVPECL
MM
Reserved
ML
LVDS—Low Swing
LH
CMOS
LM
Disable
LL
Reserved
O
—
GND
Multi
—
Supply
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Clock Output 2.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML com-
patible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
No Connect.
Leave floating. Make no external connections to this pin for
normal operation.
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
46
Rev. 1.0