SI5315B-C-GM Datasheet, PDF (16/54 Pages) Silicon Laboratories – SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER

Si5315
4. Functional Description
Crystal or
Reference Clock
Xtal/Clock
XB
XA
PLL Bypass
CKIN1+
2
CKIN1–
CKIN2+
2
CKIN2–
0
f3
1
LOS1
LOS2
LOL
AUTOSEL
CS/CA
RST
BWSEL[1:0]
FRQSEL[3:0]
FRQTBL
Signal Detect
Control
Bandwidth
Control
Frequency
Control
DSPLL^®
0
fOSC
1
0
1
2
CKOUT1+
CKOUT1–
SFOUT[1:0]
2
CKOUT2+
CKOUT2–
DBL2_BY
VDD (1.8, 2.5, or 3.3 V)
GND
Figure 7. Detailed Block Diagram
4.1. Overview
The Si5315 is a jitter-attenuating precision clock multiplier for Synchronous Ethernet, SONET/SDH, and PDH
(T1/E1) applications. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz and generates two
frequency-multiplied clock outputs ranging from 8 kHz to 644.53 MHz. The two input clocks are at the same
frequency and the two output clocks are at the same frequency. The input clock frequency and clock multiplication
ratio are selectable from a look up table of popular SyncE and T1/E1 rates.
The Si5315 is based on Silicon Laboratories' 3rd-generation DSPLL^® technology, which provides any-frequency
synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and
loop filter components. The Si5315 PLL loop bandwidth is selectable via the BWSEL[1:0] pins and supports a
range from 60 to 8.4 kHz.
The Si5315 supports hitless switching between the two input clocks in compliance with ITU-T G.8262 and Telcordia
GR-253-CORE and GR-1244-CORE. This feature greatly minimizes the propagation of phase transients to the
clock outputs during an input clock transition (<200 ps typ). Manual and automatic revertive and non-revertive input
clock switching options are available via the AUTOSEL input pin. The Si5315 monitors both input clocks for loss-of-
signal and provides a LOS alarm when it detects missing pulses on either input clock. The device monitors the lock
status of the PLL. The lock detect algorithm works by continuously monitoring the phase of the input clock in
relation to the phase of the feedback clock. The Si5315 provides a holdover capability that allows the device to
continue generation of a stable output clock when the selected input reference is lost.
The Si5315 has two differential clock outputs. The signal format of the clock outputs is programmable to support
LVPECL, LVDS, CML, or CMOS loads. The second clock output can be powered down to minimize power
consumption. For system-level debugging, a bypass mode is available which drives the output clock directly from
the input clock, bypassing the internal DSPLL. The device operates from a single 1.8, 2.5, or 3.3 V supply.
16
Rev. 1.0