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SI5315B-C-GM Datasheet, PDF (5/54 Pages) Silicon Laboratories – SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER | |||
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Si5315
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = â40 to 85 ºC)
Parameter
Symbol
Test Condition
Min Typ Max Units
Single-ended Input Voltage
Swing
VISE
fCKIN < 212.5 MHz
See Figure 2.
0.2
â
â
VPP
fCKIN > 212.5 MHz
See Figure 2.
0.25 â
â
VPP
Differential Input
Voltage Swing
VID
fCKIN < 212.5 MHz
0.2
â
â
VPP
See Figure 2.
fCKIN > 212.5 MHz
See Figure 2.
0.25 â
â
VPP
CKOUTn Output Clocks
Common Mode
VOCM
LVPECL 100 ï load
line-to-line
VDD â
â
VDD â
V
1.42
1.25
Differential Output Swing
VOD
LVPECL 100 ï load
1.1
â
1.9
VPP
line-to-line
Single Ended Output Swing
VSE
LVPECL 100 ï load
line-to-line
0.5
â
0.93
VPP
Differential Output Voltage
CKOVD
CML 100 ï load
line-to-line
350
425
500
mVPP
Common Mode
Output Voltage
CKOVCM
CML 100 ï load
line-to-line
â
VDD â
â
V
0.36
Differential
Output Voltage
CKOVD
LVDS 100 ï load
line-to-line
500
700
900
mVPP
Low swing LVDS 100 ï load 350 425 500 mVPP
line-to-line
Common Mode
Output Voltage
CKOVCM
LVDS 100 ï load
line-to-line
1.125 1.2 1.275
V
Differential Output Resistance CKORD
CML, LVPECL, LVDS,
â
200
â
ï
Disable
Output Voltage Low
Output Voltage High
CKOVOLLH
CKOVOHLH
CMOS
VDD = 1.71 V
CMOS
â
â
0.4
V
0.8 x VDD â
â
V
Notes:
1. Refers to Si5315A speed grade.
2. Refers to Si5315B speed grade.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 11.
Rev. 1.0
5
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