SI5315B-C-GM Datasheet, PDF (15/54 Pages) Silicon Laboratories – SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER

Si5315
3. System Level Overview
The Si5315 provides clock translation, jitter attenuation, and clock distribution for high-performance Synchronous
Ethernet* line card timing applications.
*Note: The Si5315 supports SyncE EEC options 1 and 2 when paired with a timing card that implements the required wander
filtering and Stratum 3 compliant reference clock. For detailed information, refer to “AN420: SyncE and IEEE 1588: Sync
Distribution for a Unified Network”.
The Si5315 provides clock translation, jitter attenuation, and clock distribution for high-performance Synchronous
Ethernet line card timing applications. The device accepts two clock inputs ranging from 8 kHz to 644.53 MHz and
generates two equal frequency, low jitter clock outputs ranging from 8 kHz to 644.53 MHz. For ease of use, the
Si5315 is pin controlled to enable simple device configuration of frequency plans, PLL loop bandwidth, and input
clock selection. The DSPLL locks to one of two input reference clocks and provides over 200 frequency
translations to synchronize output clocks for Ethernet, SONET/SDH, and PDH line cards. The Si5315 implements
internal state machines to control hitless switching between input clocks and holdover. Status alarms, loss of signal
(LOS) and loss of lock (LOL) are provided on output pins to indicate a change in device status.
This device is designed for systems with line cards that are synchronized to a redundant, centralized telecom or
Ethernet backplane. The Si5315 synchronizes to backplane clocks and generates a multiplied, jitter attenuated
Ethernet/SONET/SDH clock or PDH clock. A typical system application is shown in Figure 6. The Si5315
translates a 19.44 MHz clock from the telecom backplane to an Ethernet or SONET/SDH clock frequency to the
PHY and filters the jitter to ensure compliance with related ITU-T and Telcordia standards.
BITS A
BITS B
Redundant
Timing Cards
Wander Filtering
Hitless Switching
Holdover
Network
SynNcehtrwoonrikzaStiyonnc
PLL
Telecom
or
Ethernet
Backplane
A
B
8 kHz
19.44 MHz
25 MHz
10G LAN / WAN
SyncE Line Card
Tx Timing Path
Hitless Switching
Jitter Filtering
Frequency Translation
10GbE
PHY
A
B
Si5315
155.52 MHz
156.25 MHz
161.1328125 MHz
10GbE
PHY
Rx Timing Path
8 kHz
19.44 MHz
25 MHz
Line
Recovered
Clocks
Multi-Port
SONET / SDH / PDH Line Card
Tx Timing Path
Hitless Switching
Jitter Filtering
Frequency Translation
OC-3 / 12
A
B
Si5315
77.76 / 155.52 MHz
1.544 / 2.048 MHz
T1 / E1
Rx Timing Path
8 kHz
19.44 MHz
25 MHz
Line
Recovered
Clocks
Figure 6. Typical Si5315 Application
Rev. 1.0
15