SI5315B-C-GM Datasheet, PDF (14/54 Pages) Silicon Laboratories – SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER

Si5315
2. Typical Application Circuit
VDD = 3.3 V
System
Power
Supply
Ferrite
Bead
C4 1 µF
C3 0.1 µF
C2 0.1 µF
C1 0.1 µF
Backplane or Line
Recovered Clock
Inputs
130 
82 
130 
82 
CKIN1+
CKIN1–
VDD = 3.3 V
130 
130 
CKIN2+
CKOUT1+
CKOUT1–
CKOUT2+
CKOUT2–
0.1 µF
+
100 
–
0.1 µF
0.1 µF
+
100 
–
0.1 µF
Clock Outputs to
Ethernet PHYs
82 
82 
CKIN2–
LOS1
LOS2
CKIN1 Loss of Signal Indicator
CKIN2 Loss of Signal Indicator
Option 1:
XA
40 MHz Crystal
LOL
PLL Loss of Lock Indicator
XB
Option 2:
Ext. Refclk+
0.1 µF
Ext. Refclk–
0.1 µF
VDD
Crystal/Ref Clk
15 k
VDD 15 k
Manual/Automatic Clock ^{15 k}
Selection (L)
15 k
VDD
Input Clock Select
15 k
VDD 15 k
15 k
Frequency Table Select
15 k
VDD
Frequency Select
15 k
VDD 15 k
15 k
Bandwidth Select
15 k
VDD
Signal Format Select
15 k
VDD 15 k
Clock Output 2 Disable/ ^{15 k}
Bypass Mode Control
15 k
XA
XB
XTAL/Clock²
AUTOSEL²
CS³
FRQTBL²
FRQSEL[3:0]²
BWSEL[1:0]²
SFOUT[1:0]²
DBL2_BY²
Si5315
Reset
RST
Notes: _{1. Assumes differential LVPECL termination (3.3 V) on clock inputs.}
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
3. Assumes manual input clock selection.
Figure 5. Si5315 Typical Application Circuit
14
Rev. 1.0