SI5315B-C-GM Datasheet, PDF (43/54 Pages) Silicon Laboratories – SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER

10. Pin Descriptions: Si5315
Si5315
36 35 34 33 32 31 30 29 28
RST 1
27 FRQSEL3
FRQTBL 2
26 FRQSEL2
LOS1 3
25 FRQSEL1
LOS2 4
VDD 5
XA 6
GND
Pad
24 FRQSEL0
23 BWSEL1
22 BWSEL0
XB 7
21 _{CS_CA}
GND 8
20 GND
AUTOSEL 9
19 GND
10 11 12 13 14 15 16 17 18
Pin assignments are preliminary and subject to change.
Table 19. Si5315 Pin Descriptions
Pin #
1
Pin Name
RST
2
FRQTBL
3
LOS1
4
LOS2
I/O Signal Level
Description
I
LVCMOS External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state. Clock out-
puts are tristated during reset. After rising edge of RST sig-
nal, the Si5315 will perform an internal self-calibration when
a valid input signal is present.
This pin has a weak pull-up.
I
3-Level Frequency Table Select.
Selects frequency table. (Table 9 on page 20.)
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
O
LVCMOS CKIN1 Loss of Signal.
Active high loss-of-signal indicator for CKIN1. Once trig-
gered, the alarm will remain active until CKIN1 is validated.
0 = CKIN1 present
1 = LOS on CKIN1
O
LVCMOS CKIN2 Loss of Signal.
Active high loss-of-signal indicator for CKIN2. Once trig-
gered, the alarm will remain active until CKIN2 is validated.
0 = CKIN2 present
1 = LOS on CKIN2
Rev. 1.0
43