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SI5315B-C-GM Datasheet, PDF (53/54 Pages) Silicon Laboratories – SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING CLOCK MULTIPLIER | |||
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DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
ï® Expanded/added numerous operating sections to
initial data sheet
Revision 0.2 to Revision 0.25
ï® Updated features and application list
ï® Updated Section 1. "Electrical Specificationsâ
ï® Added voltage regulator block to Figure 7
ï® Revised footnotes in Table 9
ï® Removed plan #203 from Table 9
ï® Removed Figure 17. Crystal Oscillator with
Feedback Resistor diagram from Section 7.
"Crystal/Reference Clock Inputâ
ï® Added XA/XB jitter transfer plot to Section 7.
"Crystal/Reference Clock Inputâ
ï® Added PSRR transfer function plot to Section 8.
"Power Supply Filteringâ
ï® Updated Typical phase noise plot and RMS jitter
table in Section 9. "Typical Phase Noise Plotsâ
Revision 0.25 to Revision 0.26
ï® Corrected Section 11. "Ordering Guideâ Output
Clock Frequency Range for Si5315B-C-GM to
8 kHzâ125 MHz.
Revision 0.26 to Revision 1.0
ï® Updated Table 2 on page 4.
ï® Updated Table 3 on page 8.
ï® Updated Table 7 on page 13.
ï® Moved âTypical Application Circuitâ to page 14.
ï® Added reference to AN591.
ï® Bypass mode not supported with CMOS outputs.
ï® Changed G.8262 compliance language.
ï® Added frequency plans 103, 129, and 130.
Si5315
Rev. 1.0
53
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