SI5326C-C-GM Datasheet, PDF (8/72 Pages) Silicon Laboratories – ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5326
Table 2. DC Characteristics (Continued)
(V_DD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
3-Level Input Pins⁴
Input Voltage Low
Input Voltage Mid
Input Voltage High
Input Low Current
Input Mid Current
Input High Current
Symbol
V_ILL
V_IMM
V_IHH
I_ILL
I_IMM
I_IHH
Test Condition
See Note 4
See Note 4
See Note 4
Min
Typ
Max
Unit
—
—
0.15 x V_DD
V
0.45 x
—
0.55 x V_DD
V
V_DD
0.85 x
—
—
V
V_DD
–20
—
—
µA
–2
—
+2
µA
—
—
20
µA
LVCMOS Output Pins
Output Voltage Low
V_OL
Output Voltage Low
Output Voltage High
V_OH
Output Voltage High
Disabled Leakage
I_OZ
Current
IO = 2 mA
V_DD = 1.71 V
IO = 2 mA
V_DD = 2.97 V
IO = –2 mA
V_DD = 1.71 V
IO = –2 mA
V_DD = 2.97 V
RSTb = 0
—
—
—
—
V_DD –
—
0.4
V_DD –
—
0.4
–100
—
0.4
V
0.4
V
—
V
—
V
100
µA
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal V_DD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx
Family Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
8
Rev. 1.0