SI5326C-C-GM Datasheet, PDF (34/72 Pages) Silicon Laboratories – ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5326
Register 21.
Bit
D7
D6
Name INCDEC_
PIN
Type
R/W
Force 1
Reset value = 1111 1111
D5
D4
D3
Reserved
R
R
R
D2
D1
D0
CK1_ACTV CKSEL_
_PIN
PIN
R
R/W
R/W
Bit
Name
Function
7 INCDEC_PIN INCDEC_PIN.
Determines how coarse skew adjustments can be made. The adjustments can be made
via hardware using the INC/DEC pins or via software using the CLAT register.
0: INC and DEC inputs ignored; use CLAT register to adjust skew.
1: INC and DEC inputs control output phase increment/decrement.
6:2
Reserved Reserved.
1 CK1_ACTV_ CK1_ACTV_PIN.
PIN
The CK1_ACTV_REG status bit can be reflected to the CS_CA output pin using the
CK1_ACTV_PIN enable function. CK1_ACTV_PIN is of consequence only when pin con-
trolled clock selection is being used. (See CKSEL_PIN)
0: CS_CA output pin tristated.
1: Clock Active status reflected to output pin.
0 CKSEL_PIN CKSEL_PIN.
If manual clock selection is being used, clock selection can be controlled via the
CKSEL_REG[1:0] register bits or the CS_CA input pin. This bit is only active when
AUTOSEL_REG = Manual.
0: CS_CA pin is ignored. CKSEL_REG[1:0] register bits control clock selection.
1: CS_CA input pin controls clock selection.
34
Rev. 1.0