SI5326C-C-GM Datasheet, PDF (1/72 Pages) Silicon Laboratories – ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5326
ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER
ATTENUATOR
Features
 Generates any frequency from 2 kHz  Dual clock outputs with selectable
to 945 MHz and select frequencies to signal format
1.4 GHz from an input frequency of  Support for ITU G.709 and custom
2 kHz to 710 MHz
FEC ratios (255/238, 255/237,
 Ultra-low jitter clock outputs with jitter 255/236)
generation as low as 0.3 ps rms  LOL, LOS, FOS alarm outputs
(50 kHz–80 MHz)
 Digitally-controlled output phase
 Integrated loop filter with selectable adjustment
loop bandwidth (60 Hz to 8.4 kHz) _{ I}²_{C or SPI programmable}
 Meets OC-192 GR-253-CORE jitter _{ On-chip voltage regulator for}
specifications
1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%
 Dual clock inputs with manual or
operation
automatically controlled hitless
 Small size: 6 x 6 mm 36-lead QFN
switching (LVPECL, LVDS, CML, _{ Pb-free, ROHS compliant}
CMOS)
Applications
 SONET/SDH OC-48/OC-192/STM-  Optical modules
16/STM-64 line cards
 Wireless basestations
 ITU G.709 and custom FEC line  Data converter clocking
cards
 xDSL
 GbE/10GbE, 1/2/4/8/10G Fibre
 PDH clock synthesis
Channel line cards
 Test and measurement
 GbE/10GbE Synchronous Ethernet  Broadcast video
Description
The Si5326 is a jitter-attenuating precision clock multiplier for applications
requiring sub 1 ps jitter performance. The Si5326 accepts two input clocks ranging
from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to
945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down
separately from a common source. The Si5326 can also use its crystal oscillator
as a clock source for frequency synthesis. The device provides virtually any
frequency translation combination across this operating range. The Si5326 input
clock frequency and clock multiplication ratio are programmable through an I²C or
SPI interface. The Si5326 is based on Silicon Laboratories' 3rd-generation
DSPLL^® technology, which provides frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need for external VCXO and
loop filter components. The DSPLL loop bandwidth is digitally programmable,
providing jitter performance optimization at the application level. Operating from a
single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock
multiplication and jitter attenuation in high performance timing applications.
Ordering Information:
See page 65.
Pin Assignments
36 35 34 33 32 31 30 29 28
RST 1
27 SDI
NC 2
26 A2_SS
INT_C1B 3
25 A1
C2B 4
VDD 5
XA 6
GND
Pad
24 A0
23 SDA_SDO
22 SCL
XB 7
GND 8
21 CS_CA
20 INC
NC 9
19 DEC
10 11 12 13 14 15 16 17 18
Rev. 1.0 9/10
Copyright © 2010 by Silicon Laboratories
Si5326