SI5326C-C-GM Datasheet, PDF (17/72 Pages) Silicon Laboratories – ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

3. Typical Application Circuit
C4 1 µF
VDD = 3.3 V
System
Power
Supply
Ferrite
Bead
130 
82 
130 
82 
CKIN1+
CKIN1–
C1 0.1 µF
C2 0.1 µF
C3 0.1 µF
CKOUT1+
CKOUT1–
Input
Clock
Sources*
VDD = 3.3 V
130 
82 
130 
82 
CKIN2+
CKIN2–
Option 1:
Crystal
Crystal/Ref Clk Rate
Option 2:
Refclk+
Refclk–
Control Mode (L)
XA
VDD
15 k
15 k
XB
RATE[1:0]²
0.1 µF
XA
0.1 µF
XB
CMODE
Si5326
CKOUT2+
CKOUT2–
INC
DEC
INT_C1B
C2B
LOL
A[2:0]
SDA
SCL
CS_CA
0.1 µF
+
100 
–
0.1 µF
0.1 µF
+
100 
–
0.1 µF
Output Phase Control
Clock Outputs
Interrupt/CKIN1 Invalid Indicator
CKIN2 Invalid Indicator
PLL Loss of Lock Indicator
Serial Port Address
Serial Data
Serial Clock
I2C Interface
Clock Select/Clock Active
Reset
RST
Notes: 1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
3. I²C-required pull-up resistors not shown.
Figure 4. Si5326 Typical Application Circuit (I²C Control Mode)
Note: For an example schematic and layout, refer to the Si5325/26-EVB User’s Guide.
Input
Clock
Sources*
VDD = 3.3 V
System
Power
Supply
130 
130 
Ferrite
Bead
82 
82 
CKIN1+
CKIN1–
VDD = 3.3 V
130 
130 
CKIN2+
C4 1 µF
C1 0.1 µF
C2 0.1 µF
C3 0.1 µF
CKOUT1+
CKOUT1–
CKOUT2+
CKOUT2–
INC
DEC
0.1 µF
+
100 
–
0.1 µF
0.1 µF
+
100 
–
0.1 µF
Output Phase Control
Clock Outputs
82 
82 
CKIN2–
INT_C1B
Si5326
C2B
Interrupt/CLKIN1 Invalid Indicator
CLKIN2 Invalid Indicator
Option 1:
Crystal
Crystal/Ref Clk Rate
Option 2:
Refclk+
Refclk–
Control Mode (H)
Reset
XA
LOL
PLL Loss of Lock Indicator
VDD
15 k
15 k
XB
RATE[1:0]²
0.1 µF
XA
0.1 µF
XB
SS
SDO
SDI
SCLK
Slave Select
Serial Data Out
Serial Data In
Serial Clock
SPI Interface
CMODE
CS_CA
Clock Select/Clock Active
RST
Notes: 1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
Figure 5. Si5326 Typical Application Circuit (SPI Control Mode)
Note: For an example schematic and layout, refer to the Si5325/26-EVB User’s Guide.
Si5326
Rev. 1.0
17