SI5326C-C-GM Datasheet, PDF (30/72 Pages) Silicon Laboratories – ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5326
Register 11.
Bit
D7
D6
D5
D4
D3
D2
Name
Reserved
Type
R
Reset value = 0100 0000
Bit
Name
Function
7:2
Reserved Reserved.
1
PD_CK2 PD_CK2.
This bit controls the powerdown of the CKIN2 input buffer.
0: CKIN2 enabled
1: CKIN2 disabled
0
PD_CK1 PD_CK1.
This bit controls the powerdown of the CKIN1 input buffer.
0: CKIN1 enabled
1: CKIN1 disabled
D1
PD_CK2
R/W
D0
PD_CK1
R/W
Register 16.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
CLAT [7:0]
Type
R/W
Reset value = 0000 0000
Bit
Name
Function
7:0 CLAT [7:0] CLAT [7:0].
With INCDEC_PIN = 0, this register sets the phase delay for CKOUTn in units of
1/Fosc. This can take as long as 20 seconds.
01111111 = 127/Fosc (2s compliment)
00000000 = 0
10000000 = -128/Fosc (2s compliment)
If NI_HS[2:0] = 000, increasing CLAT does not work.
30
Rev. 1.0