SI5326C-C-GM Datasheet, PDF(5/72 Page) Silicon Laboratories – ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

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SI5326C-C-GM Datasheet, PDF (5/72 Pages) Silicon Laboratories – ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

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Si5326

Table 2. DC Characteristics

(VDD = 1.8 Â± 5%, 2.5 Â±10%, or 3.3 V Â±10%, TA = â40 to 85 Â°C)

Parameter

Supply Current1

Symbol

Test Condition

Min

Typ

IDD

LVPECL Format

251

622.08 MHz Out

Both CKOUTs Enabled

LVPECL Format

622.08 MHz Out

1 CKOUT Enabled

217

CMOS Format

204

19.44 MHz Out

Both CKOUTs Enabled

CMOS Format

19.44 MHz Out

1 CKOUT Enabled

194

Disable Mode

165

Max

Unit

279

243

234

220

CKINn Input Pins2

Input Common Mode

Voltage (Input Thresh-

old Voltage)

VICM

1.8 V Â± 5%

2.5 V Â± 10%

0.9

1.4

1.7

3.3 V Â± 10%

1.1

1.95

Input Resistance

CKNRIN

Single-ended

kâ¦

Single-Ended Input

Voltage Swing

VISE

(See Absolute Specs)

Differential Input

VID

Voltage Swing

(See Absolute Specs)

fCKIN < 212.5 MHz

0.2

See Figure 1.

fCKIN > 212.5 MHz

0.25

See Figure 1.

fCKIN < 212.5 MHz

0.2

See Figure 1.

fCKIN > 212.5 MHz

0.25

See Figure 1.

VPP

Output Clocks (CKOUTn)3

Common Mode

CKOVCM LVPECL 100 ï load line- VDD â

VDD â1.25

to-line

1.42

Notes:

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal VDD â¥ 2.5 V.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx

Family Reference Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

Rev. 1.0

▷