SI5326C-C-GM Datasheet, PDF (26/72 Pages) Silicon Laboratories – ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5326
Register 6.
Bit
D7
D6
Name Reserved SLEEP
Type
R
R/W
Reset value = 0010 1101
D5
D4
D3
SFOUT2_REG [2:0]
R/W
D2
D1
D0
SFOUT1_REG [2:0]
R/W
Bit
Name
Function
7
Reserved Reserved.
6
SLEEP SLEEP.
In sleep mode, all clock outputs are disabled and the maximum amount of internal cir-
cuitry is powered down to reduce power dissipation and noise generation. This bit over-
rides the SFOUTn_REG[2:0] output signal format settings.
0: Normal operation
1: Sleep mode
5:3 SFOUT2_ SFOUT2_REG [2:0].
REG [2:0] _{Controls output signal format and disable for CKOUT2 output buffer.}
000: Reserved
001: Disable
010: CMOS (Bypass mode not supported)
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
Note: LVPECL requires a nominal V_DD  2.5 V.
2:0 SFOUT1_ SFOUT1_REG [2:0].
REG [2:0] _{Controls output signal format and disable for CKOUT1 output buffer.}
000: Reserved
001: Disable
010: CMOS (Bypass mode not supported)
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
Note: LVPECL requires a nominal V_DD  2.5 V.
26
Rev. 1.0