SI5326C-C-GM Datasheet, PDF (50/72 Pages) Silicon Laboratories – ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5326
Register 130.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
CLAT-
DIGHOLD-
PROGRESS VALID
Reserved
FOS2_INT FOS1_INT LOL_INT
Type
R
R
R
R
R
R
Reset value = 0000 0001
Bit
Name
Function
7
CLAT-
CLAT Progress.
PROGRESS _{Indicates if the last change in the CLAT register has been processed.}
0: Coarse skew adjustment not in progress.
1: Coarse skew adjustment in progress.
6
DIGHOLD- Digital Hold Valid.
VALID
Indicates if the digital hold circuit has enough samples of a valid clock to meet digital hold
specifications.
0: Indicates digital hold history registers have not been filled. The digital hold output
frequency may not meet specifications.
1: Indicates digital hold history registers have been filled. The digital hold output
frequency is valid.
5:3
Reserved Reserved.
2
FOS2_INT CKIN2 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN2 input.
1
FOS1_INT CKIN1 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN1 input.
0
LOL_INT PLL Loss of Lock Status.
0: PLL locked.
1: PLL unlocked.
50
Rev. 1.0