SI5326C-C-GM Datasheet, PDF (13/72 Pages) Silicon Laboratories – ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Table 4. AC Specifications (Continued)
(V_DD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
PLL Performance
(fin=fout = 622.08 MHz; BW=120 Hz; LVPECL)
Lock Time
t_LOCKMP Start of ICAL to of LOL
Output Clock Phase
Change
Closed Loop Jitter
Peaking
Jitter Tolerance
Phase Noise
fout = 622.08 MHz
t_{P_STEP}
J_PK
J_TOL
CKO_PN
After clock switch
f3  128 kHz
Jitter Frequency Loop
Bandwidth
1 kHz Offset
10 kHz Offset
100 kHz Offset
Min
—
—
—
5000/BW
—
—
—
1 MHz Offset
—
Subharmonic Noise
SP_SUBH Phase Noise @ 100 kHz
—
Offset
Spurious Noise
SP_SPUR
Max spur @ n x F3
—
(n  1, n x F3 < 100 MHz)
Typ
35
200
0.05
—
–106
–121
–132
–132
–88
–93
Si5326
Max
Unit
1200
ms
—
ps
0.1
dB
—
ns pk-pk
–87
–100
–104
–119
–76
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
–70
dBc
Rev. 1.0
13