SI5326C-C-GM Datasheet, PDF (31/72 Pages) Silicon Laboratories – ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5326
Register 17.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
FLAT_
VALID
FLAT [14:8]
Type
R/W
R/W
Reset value = 1000 0000
Bit
Name
Function
7 FLAT_VALID FLAT_VALID.
Before writing a new FLAT[14:0] value, this bit must be set to zero, which causes the
existing FLAT[14:0] value to be held internally for use while the new value is being writ-
ten. Once the new FLAT[14:0] value is completely written, set FLAT_VALID = 1 to enable
its use.
0: Memorize existing FLAT[14:0] value and ignore intermediate register values during
write of new FLAT[14:0] value.
1: Use FLAT[14:0] value directly from registers.
6:0 FLAT [14:8] FLAT [14:8].
Fine resolution control for overall device skew from input clocks to output clocks. Positive
values increase the skew. See DSPLLsim for details.
FLAT [14:0] is a 2’s complement number.
Register 18.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
FLAT [7:0]
Type
R/W
Reset value = 0000 0000
Bit
Name
Function
7:0 FLAT [7:0] FLAT [7:0].
Fine resolution control for overall device skew from input clocks to output clocks. Positive
values increase the skew. See DSPLLsim for details.
FLAT [14:0] is a 2’s complement number.
Rev. 1.0
31