SI5326C-C-GM Datasheet, PDF (60/72 Pages) Silicon Laboratories – ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5326
Pin # Pin Name I/O Signal Level
Description
18
LOL
O LVCMOS PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator if the
LOL_PIN register bit is set to 1.
0 = PLL locked
1 = PLL unlocked
If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by
the LOL_POL bit. The PLL lock status will always be reflected in the
LOL_INT read only register bit.
19
DEC
I
LVCMOS Skew Decrement.
A pulse on this pin decreases the input to output device skew by
1/f_OSC (approximately 200 ps). There is no limit on the range of
skew adjustment by this method.
Pin control is enabled by setting INCDEC_PIN = 1. If
INCDEC_PIN = 0, this pin is ignored and output skew is controlled
via the CLAT register.
If both INC and DEC are tied high, phase buildout is disabled and
the device maintains a fixed-phase relationship between the
selected input clock and the output clock during an input clock
switch.
See the Si53xx Family Reference Manual for more details.
This pin has a weak pull-down.
20
INC
I
LVCMOS Skew Increment.
A pulse on this pin increases the input to output device skew by
1/f_OSC (approximately 200 ps). There is no limit on the range of
skew adjustment by this method.
Pin control is enabled by setting INCDEC_PIN = 1. If
INCDEC_PIN = 0, this pin is ignored and output skew is controlled
via the CLAT register.
If both INC and DEC are tied high, phase buildout is disabled and
the device maintains a fixed-phase relationship between the
selected input clock and the output clock during an input clock
switch.
See the Si53xx Family Reference Manual for more details.
Note: INC does not increase skew if NI_HS = 4.
This pin has a weak pull-down.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.
60
Rev. 1.0