SI5326C-C-GM Datasheet, PDF (62/72 Pages) Silicon Laboratories – ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5326
Pin #
29
28
Pin Name I/O Signal Level
Description
CKOUT1– O
CKOUT1+
Multi
Output Clock 1.
Differential output clock with a frequency range of 2 kHz to 1.4 GHz.
Output signal format is selected by SFOUT1_REG register bits. Out-
put is differential for LVPECL, LVDS, and CML compatible modes.
For CMOS format, both output pins drive identical single-ended
clock outputs.
34 CKOUT2– O
35 CKOUT2+
Multi
Output Clock 2.
Differential output clock with a frequency range of 2 kHz to 1.4 GHz.
Output signal format is selected by SFOUT2_REG register bits. Out-
put is differential for LVPECL, LVDS, and CML compatible modes.
For CMOS format, both output pins drive identical single-ended
clock outputs.
36
CMODE I
LVCMOS Control Mode.
Selects I²C or SPI control mode for the Si5326.
0 = I²C Control Mode
1 = SPI Control Mode
This pin must not be NC. Tie either high or low.
See the Si53xx Family Reference Manual for details on I²C or SPI
operation.
GND PAD
GND
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.
62
Rev. 1.0