C8051T630 Datasheet, PDF (77/221 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051T630/1/2/3/4/5
Table 14.2. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
Description
ACC
0xE0
Accumulator
ADC0CF
0xBC
ADC0 Configuration
ADC0CN
0xE8
ADC0 Control
ADC0GTH
0xC4
ADC0 Greater-Than Compare High
ADC0GTL
0xC3
ADC0 Greater-Than Compare Low
ADC0H
0xBE
ADC0 High
ADC0L
0xBD
ADC0 Low
ADC0LTH
0xC6
ADC0 Less-Than Compare Word High
ADC0LTL
0xC5
ADC0 Less-Than Compare Word Low
AMX0P
0xBB
AMUX0 Positive Channel Select
B
0xF0
B Register
CKCON
0x8E
Clock Control
CLKSEL
0xA9
Clock Select
CPT0CN
0x9B
Comparator0 Control
CPT0MD
0x9D
Comparator0 Mode Selection
CPT0MX
0x9F
Comparator0 MUX Selection
DPH
0x83
Data Pointer High
DPL
0x82
Data Pointer Low
EIE1
0xE6
Extended Interrupt Enable 1
EIP1
0xF6
Extended Interrupt Priority 1
EMI0CN
0xAA
External Memory Interface Control
IDA0CN
0xB9
Current Mode DAC0 Control
IDA0H
0x97
Current Mode DAC0 High
IDA0L
0x96
Current Mode DAC0 Low
IE
0xA8
Interrupt Enable
IP
0xB8
Interrupt Priority
IT01CF
0xE4
INT0/INT1 Configuration
OSCICL
0xB3
Internal Oscillator Calibration
OSCICN
0xB2
Internal Oscillator Control
OSCLCN
0xE3
Low-Frequency Oscillator Control
OSCXCN
0xB1
External Oscillator Control
P0
0x80
Port 0 Latch
P0MASK
0xFE
Port 0 Mask Configuration
Page
70
37
39
40
40
38
38
41
41
44
70
170
102
59
60
62
69
69
85
86
75
50
51
51
83
84
88
103
104
105
107
121
119
Rev. 1.0
77