C8051T630 Datasheet, PDF (56/221 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051T630/1/2/3/4/5
SFR Definition 10.1. REG0CN: Voltage Regulator Control
Bit
7
6
5
4
3
2
1
0
Name ^{STOPCF BYPASS}
MPCE
Type ^R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC7
Bit Name
Function
7 STOPCF _{Stop Mode Configuration.}
This bit configures the regulator’s behavior when the device enters STOP mode.
0: Regulator is still active in STOP mode. Any enabled reset source will reset the
device.
1: Regulator is shut down in STOP mode. Only the RST pin or power cycle can reset
the device.
6 BYPASS _{Bypass Internal Regulator.}
This bit places the regulator in bypass mode, turning off the regulator, and allowing the
core to run directly from the V_DD supply pin.
0: Normal Mode—Regulator is on.
1: Bypass Mode—Regulator is off, and the microcontroller core operates directly from
the V_DD supply voltage.
IMPORTANT: Bypass mode is for use with an external regulator as the supply
voltage only. Never place the regulator in bypass mode when the V_DD supply
voltage is greater than the specifications given in Table 5.1 on page 23. Doing so
may cause permanent damage to the device.
5:1 Reserved Reserved. Must Write 00000b
0 MPCE _{Memory Power Controller Enable.}
This bit can help the system save power at slower system clock frequencies (about
2.0 MHz or less) by automatically shutting down the EPROM memory between clocks
when information is not being fetched from the EPROM memory.
0: Normal Mode—Memory power controller disabled (EPROM memory is always on).
1: Low Power Mode—Memory power controller enabled (EPROM memory turns on/off
as needed).
Note: If an external clock source is used with the Memory Power Controller enabled, and the
clock frequency changes from slow (<2.0 MHz) to fast (> 2.0 MHz), the EPROM power
will turn on, and up to 20 clocks may be "skipped" to ensure that the EPROM power is
stable before reading memory.
56
Rev. 1.0