C8051T630 Datasheet, PDF (109/221 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051T630/1/2/3/4/5
20. Port Input/Output
Digital and analog resources are available through 17 I/O pins. Port pins P0.0-P1.7 can be defined as gen-
eral-purpose I/O (GPIO), assigned to one of the internal digital resources,Para1 or assigned to an analog
function as shown in Figure 20.3. Port pin P2.0 on can be used as GPIO and is shared with the C2 Inter-
face Data signal (C2D). The designer has complete control over which functions are assigned, limited only
by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a
Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding
Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 20.3 and Figure 20.4). The registers XBR0 and XBR1, defined in SFR Definition 20.1 and SFR
Definition 20.2, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 20.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Table 5.3 on page 25.
XBR0, XBR1,
PnSKIP Registers
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
Highest
Priority
Lowest
Priority
2
UART
Priority
Decoder
External Interrupts
EX0 and EX1
PnMDOUT,
PnMDIN Registers
4
SPI
2
SMBus
CP0
2
Outputs
P0.0
Digital
Crossbar
8
P0
I/O
Cells
P0.7
SYSCLK
PCA
4
2
T0, T1
8
P1
I/O
Cells
P1.0
P1.7
8
P0 _(P0.0-P0.7)
8
P1 _(P1.0-P1.7)
P2
I/O
P2.0
Cell
1
P2
(P2.0)
To Analog Peripherals
(ADC0, CP0, VREF, EXTCLK)
Figure 20.1. Port I/O Functional Block Diagram
Rev. 1.0
109