C8051T630 Datasheet, PDF (33/221 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051T630/1/2/3/4/5
6. 10-Bit ADC (ADC0, C8051T630/2/4 only)
ADC0 on the C8051T630/2/4 is a 500 ksps, 10-bit successive-approximation-register (SAR) ADC with
integrated track-and-hold, a gain stage programmable to 1x or 0.5x, and a programmable window detector.
The ADC is fully configurable under software control via Special Function Registers. The ADC may be con-
figured to measure various different signals using the analog multiplexer described in Section “6.5. ADC0
Analog Multiplexer (C8051T630/2/4 only)” on page 43. The voltage reference for the ADC is selected as
described in Section “9. Voltage Reference Options” on page 52. The ADC0 subsystem is enabled only
when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in
low power shutdown when this bit is logic 0.
ADC0CN
From
AMUX0
X1 or
AIN
X0.5
AMP0GN0
VDD
10-Bit
SAR
ADC
000
Start
Conversion ⁰⁰¹
010
011
100
101
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
Timer 3 Overflow
ADC0LTH ADC0LTL
AD0WINT
Window
Compare
32 _Logic
ADC0CF
ADC0GTH ADC0GTL
Figure 6.1. ADC0 Functional Block Diagram
Rev. 1.0
33