C8051T630 Datasheet, PDF (18/221 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051T630/1/2/3/4/5
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051T630/1/2/3/4/5
Name Pin
V_DD
3
GND
2
RST/
4
Type
D I/O
Description
Power Supply Voltage.
Ground.
Device Reset. Open-drain output of internal POR or V_DD monitor. An
external source can initiate a system reset by driving this pin low for at
least 10 µs.
C2CK
P2.0/
5
D I/O
D I/O
Clock signal for the C2 Debug Interface.
Port 2.0.
C2D
P0.0/
1
D I/O Bi-directional data signal for the C2 Debug Interface.
D I/O or Port 0.0.
A In
VREF
P0.1
20
A In
External VREF input.
D I/O or Port 0.1.
A In
IDA0
P0.2/
19
AOut IDA0 Output.
D I/O or Port 0.2.
A In
V_PP
P0.3/
18
A In
V_PP Programming Supply Voltage
D I/O or Port 0.3.
A In
EXTCLK
P0.4
17
P0.5
16
P0.6/
15
CNVSTR
A I/O or External Clock Pin. This pin can be used as the external clock input for
D In
CMOS, capacitor, or RC oscillator configurations.
D I/O or Port 0.4.
A In
D I/O or Port 0.5.
A In
D I/O or Port 0.6.
A In
D In
ADC0 External Convert Start or IDA0 Update Source Input.
18
Rev. 1.0