C8051T630 Datasheet, PDF (7/221 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051T630/1/2/3/4/5
List of Figures
1. System Overview
Figure 1.1. C8051T630/1/2/3/4/5 Block Diagram .................................................... 16
3. Pin Definitions
Figure 3.1. QFN-20 Pinout Diagram (Top View) ..................................................... 20
4. QFN-20 Package Specifications
Figure 4.1. QFN-20 Package Drawing .................................................................... 21
Figure 4.2. QFN-20 Recommended PCB Land Pattern .......................................... 22
5. Electrical Characteristics
Figure 5.1. Normal Mode Digital Supply Current vs. Frequency (MPCE = 1) ......... 32
Figure 5.2. Idle Mode Digital Supply Current vs. Frequency (MPCE = 1) ............... 32
6. 10-Bit ADC (ADC0, C8051T630/2/4 only)
Figure 6.1. ADC0 Functional Block Diagram ........................................................... 33
Figure 6.2. 10-Bit ADC Track and Conversion Example Timing ............................. 35
Figure 6.3. ADC0 Equivalent Input Circuits ............................................................. 36
Figure 6.4. ADC Window Compare Example: Right-Justified Data ......................... 42
Figure 6.5. ADC Window Compare Example: Left-Justified Data ........................... 42
Figure 6.6. ADC0 Multiplexer Block Diagram .......................................................... 43
7. Temperature Sensor (C8051T630/2/4 only)
Figure 7.1. Temperature Sensor Transfer Function ................................................ 45
Figure 7.2. Temperature Sensor Error with 1-Point Calibration at 0 Celsius ........... 46
8. 10-Bit Current Mode DAC (IDA0, C8051T630/2/4 only)
Figure 8.1. IDA0 Functional Block Diagram ............................................................ 48
Figure 8.2. IDA0 Data Word Mapping ..................................................................... 49
9. Voltage Reference Options
Figure 9.1. Voltage Reference Functional Block Diagram ....................................... 53
11. Comparator0
Figure 11.1. Comparator0 Functional Block Diagram ............................................. 57
Figure 11.2. Comparator Hysteresis Plot ................................................................ 58
Figure 11.3. Comparator Input Multiplexer Block Diagram ...................................... 61
12. CIP-51 Microcontroller
Figure 12.1. CIP-51 Block Diagram ......................................................................... 63
13. Memory Organization
Figure 13.1. Memory Map ....................................................................................... 72
Figure 13.2. Program Memory Map ......................................................................... 73
18. Reset Sources
Figure 18.1. Reset Sources ..................................................................................... 95
Figure 18.2. Power-On and VDD Monitor Reset Timing ......................................... 96
19. Oscillators and Clock Selection
Figure 19.1. Oscillator Options .............................................................................. 101
20. Port Input/Output
Figure 20.1. Port I/O Functional Block Diagram .................................................... 109
Figure 20.2. Port I/O Cell Block Diagram .............................................................. 111
Figure 20.3. Crossbar Priority Decoder with No Pins Skipped .............................. 114
Rev. 1.0
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