C8051T630 Datasheet, PDF (15/221 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051T630/1/2/3/4/5
1. System Overview
C8051T630/1/2/3/4/5 devices are fully integrated, mixed-signal, system-on-a-chip MCUs. Highlighted fea-
tures are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers.
 High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
 In-system, full-speed, non-intrusive debug interface (on-chip)
 C8051F336 ISP Flash device is available for quick in-system code development
 10-bit 500 ksps Single-ended ADC with analog multiplexer and integrated temperature sensor
 10-bit Current Output DAC
 Precision calibrated 24.5 MHz internal oscillator
 8/4/2 kB of on-chip Byte-Programmable EPROM—(512 bytes are reserved on 8k version)
 768 bytes of on-chip RAM
 SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware
 Four general-purpose 16-bit timers
 Programmable Counter/Timer Array (PCA) with three capture/compare modules and Watchdog Timer
function
 On-chip Power-On Reset, V_DD Monitor, and Temperature Sensor
 On-chip Voltage Comparator
 17 Port I/O
With on-chip power-on reset, V_DD monitor, watchdog timer, and clock oscillator, the C8051T630/1/2/3/4/5
devices are truly stand-alone, system-on-a-chip solutions. User software has complete control of all
peripherals, and may individually shut down any or all peripherals for power savings.
Code written for the C8051T630/1/2/3/4/5 family of processors will run on the C8051F336 Mixed-Signal
ISP Flash microcontroller, providing a quick, cost-effective way to develop code without requiring special
emulator circuitry. The C8051T630/1/2/3/4/5 processors include Silicon Laboratories’ 2-Wire C2 Debug
and Programming interface, which allows non-intrusive (uses no on-chip resources), full speed, in-circuit
debugging using the production MCU installed in the final application. This debug logic supports inspection
of memory, viewing and modification of special function registers, setting breakpoints, single stepping, and
run and halt commands. All analog and digital peripherals are fully functional while debugging using C2.
The two C2 interface pins can be shared with user functions, allowing in-system debugging without occu-
pying package pins.
Each device is specified for 1.8–3.6 V operation over the industrial temperature range (–45 to +85 °C). An
internal LDO is used to supply the processor core voltage at 1.8 V. The Port I/O and RST pins are tolerant
of input signals up to 5 V. The C8051T630/1/2/3/4/5 are available in 20-pin QFN RoHS compliant packag-
ing. See Table 2.1 for ordering information. A block diagram is shown in Figure 1.1.
Rev. 1.0
15