SI53115 Datasheet, PDF (6/33 Pages) Silicon Laboratories – 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER

Si53115
Table 4. Clock Input Parameters
T_A = 0–70 °C; supply voltage V_DD = 3.3 V ±5%
Parameter
Symbol
Test Condition
Input High Voltage
V_IHDIF
Differential Inputs
(singled-ended measurement)
Input Low Voltage
V_IHDIF
Differential Inputs
(singled-ended measurement)
Input Common Mode Voltage
Input Amplitude—CLK_IN
Input Slew Rate—CLK_IN
V_com
V_swing
dv/dt
Common mode input voltage
Peak to Peak Value
Measured differentially
Input Duty Cycle
Measurement from differential wave
form
Input Jitter—Cycle to Cycle
Input Frequency
Input SS Modulation Rate
J_DFin
F_ibyp
F_iPLL
FiPLL
fMODIN
Differential measurement
V_DD = 3.3 V, bypass mode
V_DD = 3.3 V, 100 MHz PLL Mode
V_DD = 3.3 V, 133.33 MHz PLL Mode
Triangle Wave modulation
Min Typ Max Unit
600 700 1150 mV
Vss-
300
300
300
0.4
45
0
300 mV
1000 mV
1450 mV
8 V/ns
50
55
%
125
33
150
90
100 110
120 133.33 147
30 31.5 33
ps
MHz
MHz
MHz
kHz
6
Rev. 1.1